iverilog: A Verilog simulation and synthesis tool1

Package available in: [trunk] [8.0] [7.0]

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format.

... part of T2, get it here

URL: http://www.icarus.com/eda/verilog/

Author: David Evans yevans@virginia.edu>
Maintainer: T2 Project <t2 [at] t2-project [dot] org>

License: GPL
Status: Beta
Version: 0.8.5

Download: ftp://icarus.com/pub/eda/verilog/v0.8/ verilog-0.8.5.tar.gz

T2 source: iverilog.cache
T2 source: iverilog.desc

Build time (on reference hardware): 65% (relative to binutils)2

Installed size (on reference hardware): 2.39 MB, 39 files

Dependencies (build time detected): 00-dirtree bash binutils bison bzip2 coreutils diffutils findutils flex gawk gcc glibc grep linux-header m4 make mktemp ncurses net-tools readline sed sysfiles tar zlib

Installed files (on reference hardware): [show]

1) This page was automatically generated from the T2 package source. Corrections, such as dead links, URL changes or typos need to be performed directly on that source.

2) Compatible with Linux From Scratch's "Standard Build Unit" (SBU).